The 74373 IC is an octal transparent D-type latch with 3-state outputs, commonly used in various digital systems for temporary data storage and buffering. The IC allows data to be stored and transferred as required in the circuit, with high output drive capability and fast switching speeds.
Features
- Octal D-type transparent latch
- 3-state outputs for bus-oriented applications
- High output drive capability
- Positive-edge triggered
- Tri-state output control
Functional Description
The 74373 IC latches the data present on the inputs when the latch enable (LE) input is high, allowing data to pass through to the outputs. When the latch enable input goes low, the data present at the inputs at that time is latched and held at the outputs. The output enable (OE) input controls whether the outputs are in the high-impedance state or driving the bus.
Applications
- Data bus interfacing
- Temporary data storage
- Data latching in microprocessors and microcontrollers
- Buffering in digital systems
Pinout Table
| Pin Number | Pin Name | Description |
|---|---|---|
| 1 | OE | Output Enable (Active Low) |
| 2 | Q0 | Output 0 |
| 3 | D0 | Data Input 0 |
| 4 | D1 | Data Input 1 |
| 5 | Q1 | Output 1 |
| 6 | D2 | Data Input 2 |
| 7 | Q2 | Output 2 |
| 8 | D3 | Data Input 3 |
| 9 | Q3 | Output 3 |
| 10 | GND | Ground |
| 11 | Q4 | Output 4 |
| 12 | D4 | Data Input 4 |
| 13 | Q5 | Output 5 |
| 14 | D5 | Data Input 5 |
| 15 | Q6 | Output 6 |
| 16 | D6 | Data Input 6 |
| 17 | Q7 | Output 7 |
| 18 | D7 | Data Input 7 |
| 19 | LE | Latch Enable (Active High) |
| 20 | VCC | Supply Voltage |
Operating Conditions
| Parameter | Symbol | Min | Max | Unit |
|---|---|---|---|---|
| Supply Voltage | Vcc | 4.5 | 5.5 | V |
| Input High Voltage | Vih | 2.0 | V | |
| Input Low Voltage | Vil | 0.8 | V | |
| Output High Voltage | Voh | 2.4 | V | |
| Output Low Voltage | Vol | 0.4 | V | |
| Input Clamp Voltage | VIK | -1.5 | V | |
| Operating Temperature | Ta | 0 | 70 | °C |
Timing Characteristics
| Parameter | Symbol | Min | Max | Unit |
|---|---|---|---|---|
| Propagation delay, LE to Q | tPLH/tPHL | 3 | 15 | ns |
| Propagation delay, OE to Q | tPZH/tPZL | 3 | 15 | ns |
| Output Disable Time, OE to Q | tPHZ/tPLZ | 2 | 12 | ns |
Truth Table
| LE | OE | D | Q (Current) | Q (Next) |
|---|---|---|---|---|
| L | X | X | Q | Q |
| H | L | 0 | Q | 0 |
| H | L | 1 | Q | 1 |
| X | H | X | Q | Z |
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